ITx Rutherford 2019 Programme

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Benchmarking a Machine Vision Image Classifier Implementation on FPGA Using Binarized Neural Network

Wednesday 3:20pm - 3:50pm, CITRENZ (Catalyst Room 5)

The current proliferation of AI into many application domains has been driving a shift away from traditionally implementing AI algorithms in software (using general-purpose processors and GPUs) towards implementation directly into hardware. This recently led to the advent of the “AI-on-Chip / AI Architectures” era.

In this paper, we demonstrate the performance advantages justifying this shift. For the sake of comparison, we have benchmarked the classification of sample images, extracted from a German Road Signs Dataset, using BNN (Binarized Neural Network) algorithm, utilizing two different platforms; running it first in software conventionally on an embedded ARM processor, then implementing it directly in hardware on an FPGA (Field Programmable Gate Array) chip. Hence, the aim of this paper is two-fold; to quantitatively measure and compare the Inference Time (time needed to classify an image) on these two different platforms, followed by highlighting its resulting impact on the future direction of AI research here in New Zealand. The resulting benchmarks show that running this image classifier directly on FPGA increased the performance when compared to running on the embedded ARM processor, by a magnitude of almost 500-fold.


Firas Al-Ali


Firas has been working in ICT since 1991, in various roles within the industry and academia, and in many countries overseas. He was Technical Training Consultant with Hewlett Packard Asia Pacific and NEC Malaysia.

Now, he is Lecturer in Computing Infrastructure, Hardware and Networks at MIT in Auckland. He holds an M.Sc. in Microprocessor Design from Massey University where he used to be Assistant Lecturer.

His current focus is research and collaboration (within NZ and overseas) in the areas of Computer Architecture, HPC and Supercomputing-on-Chip, Reconfigurable Logic and FPGA Design, AI-on-Chip, and Quantum Computing. He is currently a doctoral candidate for the Doctor of Professional Practice (Computer Engineering) at Otago Polytechnic and also the founder and leader of the FPGA AI Research (FAR) team at MIT.